The present invention relates to a memory interleave system which realizes efficient memory access in a computer system.
FIG. 6 shows an example of the arrangement of a conventional memory interleave system.
The conventional memory interleave system shown in FIG. 6 is comprised of a vector computing unit (CPU) 101 which outputs eight vector elements V0 to V7, a leading element address, and an inter-element distance and generates a memory request for each vector element, a main storage unit 102 comprised of a plurality of memory banks 121, and a memory access control unit 103 which independently performs access control on each memory bank 121 between the vector computing unit 101 and the main storage unit 102 on the basis of a memory request.
The memory access control unit 103 further includes an adder unit 104, routing address generating unit 105, contention arbitration unit 106, and crossbar unit 107. The adder unit 104 adds the leading element address and inter-element distance sent from the vector computing unit 101 to generate the memory access address of a memory request for each vector element. The routing address generating unit 105 calculates the exclusive-OR between one bit of a routing address which is part of a memory access address and one bit other than the routing address of the memory access address for each vector element, and replaces one bit of the routing address with the resultant value, thereby generating a new routing address. The contention arbitration unit 106 performs contention arbitration between memory requests for each memory bank 121 in accordance with the new routing address. The crossbar unit 107 accesses the memory banks 121 in accordance with the contention arbitration.
In this manner, the bank interleave mode is made variable (for detailed information, see, for example, Japanese Patent Laid-Open No. 2002-342306).
The conventional memory interleave system, however, cannot improve deterioration in performance due to memory bank contention between the memory requests issued by a plurality of CPUs.